EDN

SynaptiCAD offers a Free High Performance Verilog 2001 simulator

For a limited time, SynaptiCAD will be giving away free “no strings attached” 6 month licenses for VeriLogger Extreme, a high-performance compiled-code Verilog 2001 simulator that significantly ...
EDN

SIMULATION: Verilog simulator becomes open-source item

Santa Cruz, Calif. — In the 1990s, Elliot Mednick pioneered low-cost Verilog simulation. Now he's made his VeriWell simulator a free, open-source offering available through the Sourceforge Web site.
Ars Technica

Open Source VHDL (or similar) CPU Simulation Software

Hey all, my last semester of college we had to develop the microarchitecture for a RISC processor. My group was ultimately unsuccessful (our L2 cache had some serious issues), but I wouldn't mind ...
Electronic Design

What’s the Difference Between VHDL, Verilog, and SystemVerilog?

Designers of electronic hardware describe the behavior and structure of system and circuit designs using hardware description languages (HDLs)—specialized programming languages commonly known as VHDL, ...