Semiconductor Engineering

Interface DRC Can Streamline Chip-Level Interface Physical Verification

In most design companies, the chip-level physical implementation teams responsible for design floorplanning in place and route (P&R) environments also manage top-level physical verification from the ...
EDN

High-speed interfaces get PHY verification

EDA start-up Knowlent Corp is offering a product to speed verification of the PHY (physical layer) of high-speed interfaces implemented in IC designs. The Opal simulation and debugging environment ...
Design-Reuse

Knowlent Alleviates XAUI Interface Electrical Verification Bottleneck with New Opal XAUI EVP

June 8, 2005 - Santa Clara, California - Knowlent Corporation, a Silicon Valley-based Electronic Design Automation (EDA) and Intellectual Property (IP) startup, today announced that it has added XAUI ...
Design-Reuse

Secrets of M-PHY Verification

We at Arrow Devices are committed to help developers build fast and robust standard interface IP. We have prepared the following actionable questionnaire and downloadable test plan for MIPI M-PHY v2.0 ...