Design-Reuse

Dolphin Integration's live webinar on Power, Performance and Area optimization during SoC physical implementation

This live webinar will be broadcasted on November 19, 2015. Why is Dolphin Integration in the best position to deliver this webinar? Dolphin Integration’s expertise in RTL-to-GDSII and RTL-to-Fab is ...
Design-Reuse

Dolphin Integration introduces a new Panoply of Silicon IPs for reducing the 65 nm silicon area up to 10%

Meylan, France – June 25, 2010. Designers of cost-optimized SoCs now can take advantage of the High Density Panoply to increase the density of their SoC up to 10%. The Dolphin Integration High ...